View CY7C10612G30-10ZSXI_9039433.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy7c10612g cy7c10612ge 16-mbit (1m 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-88702 rev. *f revised january 3, 2018 16-mbit (1m 16) static ram features high speed ? t aa = 10 ns embedded error-correcting code (ecc) for single-bit error correction low active power ? i cc = 90 ma typical low cmos standby power ? i sb2 = 20 ma typical operating voltages of 3.3 0.3 v 1.0 v data retention transistor-transistor logic (ttl) compatible inputs and outputs err pin to indicate 1-bit error detection and correction available in pb-free 54-pin tsop ii package functional description the cy7c10612g and cy7c10612ge are high performance cmos fast static ram device s with embedded ecc. these devices are offered in single chip enable option. the cy7c10612ge device includes an error indication pin that signals an error-detection and correction event during a read cycle. to write to the device, take chip enables (ce ) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 19 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 19 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see truth table on page 14 for a complete description of read and write modes. the input or output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low and we low). on the cy7c10612ge devices the detection and correction of a single-bit error in the accessed location is indicated by the assertion of the err output (err = high). see the truth table on page 14 for a complete description of read and write modes. the cy7c10612g and cy7c10612ge are available in a 54-pin tsop ii package. for a complete list of related documentation, click here . selection guide description - 10 unit maximum access time 10 ns maximum operating current 110 ma maximum cmos standby current 30 ma
document number: 001-88702 rev. *f page 2 of 19 cy7c10612g cy7c10612ge 15 16 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 1m x 16 array a 0 a 12 a 14 a 13 a a a 17 a 18 a 10 a 11 i/o 0 ? i/o 7 oe i/o 8 ? i/o 15 ce we ble bhe a 9 a 19 logic block diagram ? cy7c10612g logic block diagram ? cy7c10612ge
document number: 001-88702 rev. *f page 3 of 19 cy7c10612g cy7c10612ge contents pin configurations ........................................................... 4 maximum ratings ............................................................. 6 operating range ............................................................... 6 dc electrical characteristics .......................................... 6 capacitance ...................................................................... 7 thermal resistance .......................................................... 7 ac test loads and waveforms ....................................... 7 data retention characteristics ....................................... 8 data retention waveform ................................................ 8 ac switching characteristics ......................................... 9 switching waveforms .................................................... 10 truth table ...................................................................... 14 err output ? cy7c10612ge ........................................ 14 ordering information ...................................................... 15 ordering code definitions ..... .................................... 15 package diagrams .......................................................... 16 acronyms ........................................................................ 17 document conventions ................................................. 17 units of measure ....................................................... 17 document history page ................................................. 18 sales, solutions, and legal information ...................... 19 worldwide sales and design s upport ......... .............. 19 products .................................................................... 19 psoc? solutions ...................................................... 19 cypress developer community ................................. 19 technical support ................. .................................... 19
document number: 001-88702 rev. *f page 4 of 19 cy7c10612g cy7c10612ge pin configurations figure 1. 54-pin tsop ii pinout (top view) [1] cy7c10612g 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 i/o 11 18 17 20 19 23 28 25 24 22 21 27 26 v ss i/o 10 i/o 12 v cc i/o 13 i/o 14 v ss a 16 a 17 a 11 a 12 a 13 a 14 i/o 0 a 15 i/o 7 i/o 9 v cc i/o 8 i/o 15 a 19 a 4 a 3 a 2 a 1 ce v cc we nc ble nc v ss oe a 8 a 7 a 6 a 5 a 0 nc a 9 bhe a 10 10 a 18 46 45 47 50 49 48 51 54 53 52 i/o 2 i/o 1 i/o 3 v ss v cc v ss i/o 6 i/o 5 v cc i/o 4 note 1. nc pins are not connected on the die.
document number: 001-88702 rev. *f page 5 of 19 cy7c10612g cy7c10612ge figure 2. 54-pin tsop ii pinout with err (top view) [2, 3] cy7c10612ge pin configurations (continued) note 2. nc pins are not connected on the die. 3. err is an output pin. if not used, this pin should be left floating.
document number: 001-88702 rev. *f page 6 of 19 cy7c10612g cy7c10612ge maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... ............ ........... ....... ?55 ? c to +125 ? c supply voltage on v cc relative to gnd [4] .................. ?0.5 v to v cc + 0.5 v dc voltage applied to outputs in high z state [4] ................................. ?0.5 v to v cc + 0.5 v dc input voltage [4] ............................. ?0.5 v to v cc + 0.5 v current into outputs (low) .... .................................... 20 ma static discharge voltage (mil-std-883, method 3015) ..... ............................> 2001 v latch up current ................................................... > 200 ma operating range range ambient temperature v cc industrial ?40 ? c to +85 ? c 3.3 v ? 0.3 v dc electrical characteristics over the operating range of ?40 ? c to 85 ? c parameter description test conditions 10 ns unit min typ [5] max v oh output high voltage 2.2 v to 2.7 v v cc = min, i oh = ?4.0 ma 2.2 ? ? v 2.7 v to 3.0 v v cc = min, i oh = ?4.0 ma 2.4 ? ? v ol output low voltage v cc = min, i ol = 8 ma ? ? 0.4 v v ih [4] input high voltage ? 2.0 ? v cc + 0.3 v v il [4] input low voltage ? ?0.3 ? 0.8 v i ix input leakage current gnd < v in < v cc ?1.0 ? +1.0 ? a i oz output leakage current gnd < v out < v cc , output disabled ?1.0 ? +1.0 ? a i cc operating supply current v cc = max, i out = 0 ma, cmos levels f = 100 mhz ? 90.0 110.0 ma f = 66.7 mhz ? 70.0 80.0 ma i sb1 automatic ce power-down current ? ttl inputs max v cc , ce > v ih [5] , v in > v ih or v in < v il , f = f max ??40.0ma i sb2 automatic ce power-down current ? cmos inputs max v cc , ce > v cc ? 0.2 v [5] , v in > v cc ? 0.2 v or v in < 0.2 v, f = 0 ? 20.0 30.0 ma notes 4. v il(min) = ?2.0 v and v ih(max) = v cc + 2 v for pulse durations of less than 20 ns. 5. typical values are included only for reference and are not guaranteed or tested. typical values are measured at v cc = 1.8 v (for a v cc range of 1.65 v?2.2 v), v cc = 3 v (for a v cc range of 2.2 v?3.6 v), and v cc = 5 v (for a v cc range of 4.5 v?5.5 v), t a = 25 c.
document number: 001-88702 rev. *f page 7 of 19 cy7c10612g cy7c10612ge capacitance parameter [6] description test conditions 54-pin tsop ii unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 10 pf c out i/o capacitance thermal resistance parameter [6] description test conditions 54-pin tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 93.63 ? c/w ? jc thermal resistance (junction to case) 21.58 notes 6. tested initially and after any design or proces s changes that may affect these parameters. 7. full-device ac operation assumes a 100-s ramp time from 0 to v cc (min) and 100-s wait time after v cc stabilizes to its operational value. ac test loads and waveforms figure 3. ac test loads and waveforms [7] 90% 10% 3.0 v gnd 90% 10% all input pulses 3.3 v output 5 pf* including jig and scope (b) r1 317 ? r2 351 ? rise time: fall time: > 1 v/ns (c) output 50 ? z 0 = 50 ? v th = 1.5 v 30 pf* * capacitive load consists of all components of the test environment high z characteristics: (a) > 1 v/ns
document number: 001-88702 rev. *f page 8 of 19 cy7c10612g cy7c10612ge data retention characteristics over the operating range ?45 ? c to 85 ? c parameter description conditions min typ [8] max unit v dr v cc for data retention ? 1.0 ? ? v i ccdr data retention current v cc = 2 v, ce ? v cc ? 0.2 v, v in ? v cc ? 0.2 v or v in ? 0.2 v ??30.0ma t cdr [9] chip deselect to data retention time ? 0.0 ? ? ns t r [9, 10] operation recovery time ? 10.0 ? ? ns data retention waveform figure 4. data retention waveform 3.0 v 3.0 v t cdr v dr > 1 v data retention mode t r ce v cc notes 8. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 9. this parameter is guaranteed by design and is not tested. 10. full device operation requires linear v cc ramp from v dr to v cc(min.) ? 100 ? s or stable at v cc(min.) ? 100 ? s.
document number: 001-88702 rev. *f page 9 of 19 cy7c10612g cy7c10612ge ac switching characteristics over the operating range parameter [11] description - 10 unit min max read cycle t power v cc to the first access [12] 100.0 ? s t rc read cycle time 10.0 ? ns t aa address to data valid ? 10.0 ns t oha data hold from address change 3.0 ? ns t ace ce low to data valid ? 10.0 ns t doe oe low to data valid ? 5.0 ns t lzoe oe low to low z [13, 14, 15] 0.0 ? ns t hzoe oe high to high z [13, 14, 15] ?5.0 ns t lzce ce low to low z [13, 14, 15] 3.0 ? ns t hzce ce high to high z [13, 14, 15] ?5.0 ns t pu ce low to power-up [16] 0.0 ? ns t pd ce high to power-down [16] ?10.0 ns t dbe byte enable to data valid ? 5.0 ns t lzbe byte enable to low z 1.0 ? ns t hzbe byte disable to high z ? 6.0 ns write cycle [17, 18] t wc write cycle time 10.0 ? ns t sce ce low to write end 7.0 ? ns t aw address setup to write end 7.0 ? ns t ha address hold from write end 0.0 ? ns t sa address setup to write start 0.0 ? ns t pwe we pulse width 7.0 ? ns t sd data setup to write end 5.0 ? ns t hd data hold from write end 0.0 ? ns t lzwe we high to low z [13, 14, 15] 3.0 ? ns t hzwe we low to high z [13, 14, 15] ?5.0 ns t bw byte enable to end of write 7.0 ? ns notes 11. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, and input pulse levels of 0 to 3.0 v. test conditions for the read cycle use output loading shown in part a) of figure 3 on page 7 , unless specified otherwise. 12. t power gives the minimum amount of time that the power supply is at typical v cc values until the first memory access is performed. 13. t hzoe , t hzce , t hzwe , t hzbe , t lzoe , t lzce , t lzwe , and t lzbe are specified with a load capacitance of 5 pf as in (b) of figure 3 on page 7 . transition is measured ? 200 mv from steady state voltage. 14. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 15. tested initially and after any design or process changes that may affect these parameters. 16. these parameters are guaranteed by design and are not tested. 17. the internal write time of the memory is defined by the overlap of we , ce = v il . chip enable must be active and we and byte enables must be low to initiate a write, and the transition of any of these signals can terminate. the input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 18. the minimum write cycle time for write cycle no. 2 (we controlled, oe low) is the sum of t hzwe and t sd .
document number: 001-88702 rev. *f page 10 of 19 cy7c10612g cy7c10612ge switching waveforms figure 5. read cycle no. 1 (address transition controlled) for cy7c10612g [19, 20] figure 6. read cycle no. 1 (address transition controlled) for cy7c10612ge [20, 21] previous data valid data out valid rc t aa t oha t rc address data i/o notes 19. the device is continuously selected. oe , ce = v il , bhe , ble or both = v il . 20. we is high for read cycle. 21. address valid before or similar to ce transition low.
document number: 001-88702 rev. *f page 11 of 19 cy7c10612g cy7c10612ge figure 7. read cycle no. 2 (oe controlled) [22, 23] switching waveforms (continued) t rc t hzce t pd t ace t doe t lzoe t dbe t lzbe t lzce t pu high impedance data out valid high impedance address ce oe bhe/ ble data i/o v cc supply current t hzoe t hzbe i sb notes 22. we is high for read cycle. 23. address valid before or similar to ce transition low.
document number: 001-88702 rev. *f page 12 of 19 cy7c10612g cy7c10612ge figure 8. write cycle no. 1 (ce controlled) [24, 25, 26] figure 9. write cycle no. 2 (we controlled, oe low) [24, 25, 26] switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw t data i/o address ce we bhe , ble data in valid t hd t sd t sce t ha t aw t pwe t wc t bw t sa t lzwe t hzwe data i/o address ce we bhe ,ble data in valid note 27 notes 24. data i/o is high impedance if oe , bhe , and/or ble = v ih . 25. the internal write time of the memory is defined by the overlap of we = v il , ce = v il and bhe or ble = v il . these signals must be low to initiate a write, and the high transition of any of these signals can terminate the opera tion. the input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 26. the minimum write cycle pulse width should be equal to the sum of t hzwe and t sd . 27. during this period the i/os are in output state. do not apply input signals.
document number: 001-88702 rev. *f page 13 of 19 cy7c10612g cy7c10612ge figure 10. write cycle no. 3 (ble or bhe controlled) [28, 29] switching waveforms (continued) t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble ce we data in valid note 30 notes 28. data i/o is high impedance if oe , bhe , and/or ble = v ih . 29. the internal write time of the memory is defined by the overlap of we = v il , ce = v il and bhe or ble = v il . these signals must be low to initiate a write, and the high transition of any of these signals can terminate the opera tion. the input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 30. during this period, the i/os are in output state. do not apply input signals.
document number: 001-88702 rev. *f page 14 of 19 cy7c10612g cy7c10612ge truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high z high z power-down standby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high z read lower bits only active (i cc ) l l h h l high z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high z write lower bits only active (i cc ) l x l h l high z data in write upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) err output ? cy7c10612ge output [31] mode 0 read operation, no error in the stored data. 1 read operation, single-bit error detected and corrected. high-z device deselected or outputs disabled or write operation. note 31. err is an output pin. if not used, this pin should be left floating.
document number: 001-88702 rev. *f page 15 of 19 cy7c10612g cy7c10612ge ordering code definitions ordering information speed (ns) ordering code package diagram package type (pb-free) operating range 10 CY7C10612G30-10ZSXI 51-85160 54-pin tsop ii industrial CY7C10612G30-10ZSXIt 54-pin tsop ii, tape and reel cy7c10612ge30-10zsxi 54-pin tsop ii, with err pin cy7c10612ge30-10zsxit 54-pin tsop ii, with err pin, tape and reel x = blank or t blank = bulk; t = tape and reel temperature range: i = industrial pb-free package type: zs = 54-pin tsop ii speed grade: 10 ns voltage range: 30 = 3 v to 3.6 v x = blank or e blank = without err output; e = with err output, single bit error correction indicator process technology: g = 65 nm single chip enable bus width: 1 = 16 density: 06 = 16-mbit fast asynchronous sram family technology code: c = cmos marketing code: 7 = sram company id: cy = cypress cy 10 zs 7 c 1 06 x 1 i - e 2 g 30 x
document number: 001-88702 rev. *f page 16 of 19 cy7c10612g cy7c10612ge package diagrams figure 11. 54-pin tsop ii (22.4 11.84 1.0 mm) z54-ii packa ge outline, 51-85160 51-85160 *e
document number: 001-88702 rev. *f page 17 of 19 cy7c10612g cy7c10612ge acronyms document conventions units of measure table 1. acronyms used in this document acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package ttl transistor-transistor logic we write enable table 2. units of measure symbol unit of measure c degree celsius mhz megahertz a microampere ? s microsecond ma milliampere mm millimeter mv millivolt ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
document number: 001-88702 rev. *f page 18 of 19 cy7c10612g cy7c10612ge document history page document title: cy7c10612g/cy7c10612ge, 16-mbit (1m 16) static ram document number: 001-88702 rev. ecn no. orig. of change submission date description of change *d 4865557 nile 07/31/2015 changed status from preliminary to final. *e 5437839 nile 09/15/2016 updated maximum ratings : updated note 4 (replaced ?2 ns? with ?20 ns?). updated dc electrical characteristics : removed all values corresponding to v oh parameter. included operating ranges ?2.2 v to 2.7 v? and ?2.7 v to 3.0 v? and all values corresponding to v oh parameter. updated ordering information : updated part numbers. updated ordering code definitions . updated to new template. completing sunset review. *f 6011828 aesatmp8 01/03/2018 u pdated logo a nd copyright.
document number: 001-88702 rev. *f revised january 3, 2018 page 19 of 19 ? cypress semiconductor corporation, 2013-2018. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but no t limited to, the implied warranties of me rchantability and fitness for a particular purpose. no computing device can be absolutely secure. therefore, despite security measures implemented in cypress hardware or software products, cyp ress does not assume any liability arising out of any security breach, such as unauthorized access to or use of a cypress product. in addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. it is the responsi bility of the user of this document to properly design, progra m, and test the functionality and safety of any application made of this information and any resulting product. cypress products are not designed, intended, or authorized for use as critical component s in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or system s (including resuscitation equi pment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or syst em could cause personal injury, death, or property damage (?un intended uses?). a critical component is any component of a device or system whose failure to perform can be re asonably expected to cause the failure of the device or system, or to affect its sa fety or effectiveness. cypress is not liable, in whole or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses o f cypress products. you shall indemnify and hold cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or r elated to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. cy7c10612g cy7c10612ge sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/ interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/usb wireless connectivity cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 mcu cypress developer community community | projects | video | blogs | training | components technical support cypress.com/support

▲Up To Search▲

Price & Availability of CY7C10612G30-10ZSXI

	To Download CY7C10612G30-10ZSXI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .